// -*- mode:c++ -*-

// Copyright (c) 2011,2017-2022 Arm Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
// not be construed as granting a license to any other intellectual
// property including but not limited to intellectual property relating
// to a hardware implementation of the functionality of the software
// licensed hereunder.  You may use the software subject to the license
// terms below provided that you ensure that this notice is replicated
// unmodified and in its entirety in all distributions of the software,
// modified or unmodified, in source code or in binary form.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

def template ImmOp64Declare {{
class %(class_name)s : public %(base_class)s
{
  private:
    %(reg_idx_arr_decl)s;

  public:
    // Constructor
    %(class_name)s(ExtMachInst machInst,uint64_t _imm);

    Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};

def template ImmOp64Constructor {{
    %(class_name)s::%(class_name)s(ExtMachInst machInst, uint64_t _imm) :
        %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm)
    {
        %(set_reg_idx_arr)s;
        %(constructor)s;
    }
}};

def template RegOp64Declare {{
class %(class_name)s : public %(base_class)s
{
  private:
    %(reg_idx_arr_decl)s;

  public:
    // Constructor
    %(class_name)s(ExtMachInst machInst, RegIndex _op1);

    Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};

def template RegOp64Constructor {{
    %(class_name)s::%(class_name)s(ExtMachInst machInst, RegIndex _op1) :
        %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1)
    {
        %(set_reg_idx_arr)s;
        %(constructor)s;
    }
}};

def template RegImmImmOp64Declare {{
class %(class_name)s : public %(base_class)s
{
  private:
    %(reg_idx_arr_decl)s;

  public:
    // Constructor
    %(class_name)s(ExtMachInst machInst,
                   RegIndex _op1,
                   uint64_t _imm1, uint64_t _imm2);
    Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};

def template RegImmImmOp64Constructor {{
    %(class_name)s::%(class_name)s(ExtMachInst machInst,
                                   RegIndex _op1,
                                   uint64_t _imm1, uint64_t _imm2) :
        %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
                       _op1, _imm1, _imm2)
    {
        %(set_reg_idx_arr)s;
        %(constructor)s;
    }
}};

def template RegRegImmImmOp64Declare {{
class %(class_name)s : public %(base_class)s
{
  private:
    %(reg_idx_arr_decl)s;

  public:
    // Constructor
    %(class_name)s(ExtMachInst machInst,
                   RegIndex _dest, RegIndex _op1,
                   uint64_t _imm1, uint64_t _imm2);
    Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};

def template RegRegImmImmOp64Constructor {{
    %(class_name)s::%(class_name)s(ExtMachInst machInst,
                                   RegIndex _dest, RegIndex _op1,
                                   uint64_t _imm1, uint64_t _imm2) :
        %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
                       _dest, _op1, _imm1, _imm2)
    {
        %(set_reg_idx_arr)s;
        %(constructor)s;
    }
}};

def template RegRegRegImmOp64Declare {{
class %(class_name)s : public %(base_class)s
{
  private:
    %(reg_idx_arr_decl)s;

  public:
    // Constructor
    %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1,
                   RegIndex _op2, uint64_t _imm);
    Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};

def template RegRegRegImmOp64Constructor {{
    %(class_name)s::%(class_name)s(ExtMachInst machInst, RegIndex _dest,
                                   RegIndex _op1, RegIndex _op2,
                                   uint64_t _imm) :
        %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
                       _dest, _op1, _op2, _imm)
    {
        %(set_reg_idx_arr)s;
        %(constructor)s;
    }
}};

def template MiscRegOp64Declare {{
class %(class_name)s : public %(base_class)s
{
  private:
    %(reg_idx_arr_decl)s;

  public:
    // Constructor
    %(class_name)s(ExtMachInst machInst, MiscRegIndex _dest, uint64_t _imm);

    Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};

def template MiscRegOp64Constructor {{
    %(class_name)s::%(class_name)s(ExtMachInst machInst, MiscRegIndex _dest,
                                   uint64_t _imm) :
        %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _imm)
    {
        %(set_reg_idx_arr)s;
        %(constructor)s;
    }
}};

def template MiscRegRegOp64Declare {{
class %(class_name)s : public %(base_class)s
{
  private:
    %(reg_idx_arr_decl)s;

  public:
    // Constructor
    %(class_name)s(ExtMachInst machInst, MiscRegIndex _dest,
            RegIndex _op1);

    Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};

def template MiscRegRegOp64Constructor {{
    %(class_name)s::%(class_name)s(ExtMachInst machInst, MiscRegIndex _dest,
                                   RegIndex _op1) :
        %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
                       _dest, _op1)
    {
        %(set_reg_idx_arr)s;
        %(constructor)s;
    }
}};

def template RegMiscRegOp64Declare {{
class %(class_name)s : public %(base_class)s
{
  private:
    %(reg_idx_arr_decl)s;

  public:
    // Constructor
    %(class_name)s(ExtMachInst machInst, RegIndex _dest,
            MiscRegIndex _op1);

    Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};

def template RegMiscRegOp64Constructor {{
    %(class_name)s::%(class_name)s(ExtMachInst machInst, RegIndex _dest,
                                   MiscRegIndex _op1) :
        %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
                       _dest, _op1)
    {
        %(set_reg_idx_arr)s;
        %(constructor)s;
    }
}};

def template XPauthOpRegRegDeclare {{
class %(class_name)s : public %(base_class)s
{
  private:
    bool data;
    %(reg_idx_arr_decl)s;

  public:
    // Constructor
    %(class_name)s(ExtMachInst machInst, RegIndex _dest);
    Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};

def template XPauthOpRegRegConstructor {{
    %(class_name)s::%(class_name)s(ExtMachInst machInst, RegIndex _dest) :
        %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest)
    {
        %(set_reg_idx_arr)s;
        data = bits(machInst, 10);
        %(constructor)s;
    }
}};

def template RegNoneDeclare {{
class %(class_name)s : public %(base_class)s
{
  private:
    %(reg_idx_arr_decl)s;

  public:
    // Constructor
    %(class_name)s(ExtMachInst machInst, RegIndex _dest);

    Fault execute(ExecContext *, trace::InstRecord *) const;
};
}};

def template RegNoneConstructor {{
    %(class_name)s::%(class_name)s(ExtMachInst machInst, RegIndex _dest) :
        %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest)
    {
        %(set_reg_idx_arr)s;
        %(constructor)s;
    }
}};

def template DvmTlbiDeclare {{
class %(class_name)s : public %(base_class)s
{
  private:
    %(reg_idx_arr_decl)s;
    const bool dvmEnabled;

  public:
    // Constructor
    %(class_name)s(ExtMachInst machInst, MiscRegIndex _dest,
            RegIndex _op1, bool dvm_enabled);

    Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
    Fault completeAcc(PacketPtr, ExecContext *,
                      trace::InstRecord *) const override;
    Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};

def template DvmDeclare {{
    /**
     * Static instruction class for "%(mnemonic)s".
     */
    class %(class_name)s : public %(base_class)s
    {
      private:
        %(reg_idx_arr_decl)s;
        const bool dvmEnabled;

      public:
        /// Constructor.
        %(class_name)s(ExtMachInst machInst, bool dvm_enabled);
        Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
        Fault completeAcc(PacketPtr, ExecContext *,
                          trace::InstRecord *) const override;
        Fault execute(ExecContext *, trace::InstRecord *) const override;
    };
}};

def template DvmTlbiConstructor {{
    %(class_name)s::%(class_name)s(ExtMachInst machInst, MiscRegIndex _dest,
                                   RegIndex _op1, bool dvm_enabled) :
        %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
                       _dest, _op1),
        dvmEnabled(dvm_enabled)
    {
        %(set_reg_idx_arr)s;
        %(constructor)s;

        if (dvmEnabled) {
            flags[IsLoad] = true;
        }
    }
}};

def template DvmConstructor {{
    %(class_name)s::%(class_name)s(ExtMachInst machInst, bool dvm_enabled) :
        %(base_class)s("%(mnemonic)s", machInst, %(op_class)s),
        dvmEnabled(dvm_enabled)
    {
        %(set_reg_idx_arr)s;
        %(constructor)s;

        if (dvmEnabled) {
            flags[IsLoad] = true;
        }
    }
}};

def template DvmInitiateAcc {{
    Fault
    %(class_name)s::initiateAcc(ExecContext *xc,
                                trace::InstRecord *traceData) const
    {
        Fault fault = NoFault;

        %(op_decl)s;
        %(op_rd)s;
        %(code)s;

        %(dvm_code)s;

        if (fault == NoFault) {
            %(op_wb)s;
        }
        return fault;
    }
}};

def template DvmCompleteAcc {{
    Fault
    %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
                                trace::InstRecord *traceData) const
    {
        return NoFault;
    }
}};
